This instruction adds the content of the memory word specified by the effective address to the value of AC. The same clock transition clears SC to 0, transferring control to timing signal T0 to start a new instruction cycle. The clock transition associated with the next timing signal T5 transfers to AC the result of the AND logic operation between the contents of DR and AC. The clock transition associared with timing signal T4 transfers the operand from memory into DR. The control function for this instruction uses the operation decoder D0 since this output of the decoder is active when the instruction has an AND operation whose binary code value 000. Two timing signals are needed to execute the instaruction. The microoperations that execute this instruction are: This is an instaruction that perform the AND logic operation on pairs of bits in AC and the memory word specified by the effective address. We now explain the operation of each instruction and list the control functions and microoperations needed for their execution.Ī flowchart that summarizes all the microoperations is presented at the end of this section The data must be read from memory to a register where they can be operated on with logic circuits. This is because data stored in memory cannot be processed directly. The actual execution of the instruction in the bus system will require a sequence of microoperations.
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